1. Field of the Invention
The present invention relates to a semiconductor memory device including flip-flop-type memory cells and, more particularly, to a technique for controlling the memory cell power supply.
2. Description of the Background Art
As the process rule becomes finer and finer in recent years, the circuit area and the power supply voltage of semiconductor integrated circuits have been reduced rapidly. However, with a semiconductor memory device including flip-flop-type memory cells, such as a static-type random access memory (SRAM), for example, such advancement makes the characteristics variations between transistors of the memory cells more significant. Due to such characteristics variations and to the reduced power supply voltage, it is now very difficult to realize stable memory cell characteristics, thereby lowering the production yield of semiconductor memory devices.
FIG. 13 shows an SRAM memory cell of a flip-flop type, which is formed by ordinary CMOS transistors. In FIG. 13, QN1 and QN2 are drive transistors, QN3 and QN4 are access transistors, QP1 and QP2 are load transistors, WL is a word line, BL and /BL are bit lines, and VDD is the power supply.
The load transistor QP1 and the drive transistor QN1 together form an inverter, and the load transistor QP2 and the drive transistor QN2 together form another inverter. The input/output terminals of the inverters are connected together to thereby form a flip-flop. The gate terminals of the access transistors QN3 and QN4 are connected to the word line WL, and the drain terminals thereof are connected to the bit lines BL and /BL, respectively. The source terminals of the access transistors QN3 and QN4 are connected to the input/output terminals of the inverters.
Data is written to the SRAM memory cell of FIG. 13 as follows. The bit lines BL and /BL are pre-charged to an H level. Then, the word line WL is brought from an L level to the H level (active) while the potential of one of the bit lines BL and /BL is brought from the H level to the L level.
Common memory cell characteristics of an SRAM include the write level and the static noise margin.
The write level represents the voltage with which data is written to the memory cell. Data is written to an SRAM memory cell by inverting the state of the flip-flop of the memory cell (note however that the state of the flip-flop is not inverted when the write data happens to be the same as the stored data). The critical bit line potential with which the state of the flip-flop of the memory cell can be inverted is referred to as the write level.
A lower write level gives a larger margin for erroneous writing (static noise margin) due to bit line noise, or the like, but presents a problem in that the flip-flop cannot be inverted until the bit line potential becomes sufficiently low, thereby resulting in a long write time. A higher write level gives a shorter write time, but also gives a smaller margin for erroneous writing (static noise margin).
A lower write level also means that the state of the flip-flop of the memory cell is less easily inverted due to bit line noise, or the like, in a read operation period, i.e., a larger static noise margin, and a higher write level also means that the state of the flip-flop of the memory cell is more easily inverted in a read operation period, i.e., a smaller static noise margin.
Thus, there is a trade-off between the write level and the static noise margin.
In order to solve such a problem, Japanese Laid-Open Patent Publication No. 55-64686, for example, discloses a technique for improving the write level by controlling the power supply voltage of the memory cell.
As the process rule becomes finer, there is a problem of an increased leak current flowing through transistors being OFF. Particularly, the memory cell section is often formed by transistors with small gate widths in order to reduce the area of the semiconductor memory device. A transistor with a smaller gate width, as compared with a transistor with a larger gate width, has a larger off-leak current per unit gate width.
The off-leak current flowing through a memory cell also varies depending on the arrangement of the memory cell array, the transistor characteristics (different impurity concentrations), the operating power supply voltage, the temperature condition, etc.
For example, in a write operation in a case where the power supply of a memory cell is controlled, the power supply voltage of memory cells connected to non-selected bit lines, other than the selected bit line to which data is to be written, will decrease unless there is supplied a charge sufficient to compensate for the amount of charge to be lost by the off-leak current flowing through the memory cells connected to the non-selected bit lines. Similarly, in a non-write operation period (in a read operation period), the power supply voltage of the memory cells connected to all bit lines will decrease unless there is supplied a charge sufficient to compensate for the amount of charge to be lost by the off-leak current flowing through the memory cells connected to the bit lines. If the power supply voltage of a memory cell decreases, the static noise margin of the memory cell deteriorates, whereby data in the memory cell is more likely to be corrupted (inverted).
In the configuration disclosed in FIG. 2 of Japanese Laid-Open Patent Publication No. 55-64686, the power supply voltage of the memory cell is set to a level lower than the VDD level in a non-write operation period (in a read operation period). Therefore, as described above, the static noise margin of the memory cell deteriorates, and corruption of memory cell data is more likely to occur.
In the configuration disclosed in FIG. 1 of Japanese Laid-Open Patent Publication No. 55-64686, no countermeasures are taken for the very high leak current level flowing through the memory cell, which occurs in semiconductor memory devices of the latest generation. In a write operation period, if there is a very high off-leak current through memory cells connected to non-selected bit lines other than the selected bit line to which data is to be written, there is also a substantial drop in the memory cell power supply voltage caused by the off-leak current. Therefore, the static noise margin of the memory cell deteriorates, and corruption of memory cell data is more likely to occur.
Moreover, in the configuration disclosed in FIG. 1 of Japanese Laid-Open Patent Publication No. 55-64686, since the output of the inverter including a depletion transistor and an enhancement transistor connected in series together is supplied as the power supply of the memory cell, there is always a through current in a write operation period. Moreover, the configuration employs the depletion transistor in order to compensate for the amount of charge to be lost by the off-leak current flowing through the memory cells connected to the non-selected bit lines. However, as the process rule becomes finer, there is a problem of an increased leak current flowing through transistors being OFF, as described above. Therefore, in order to compensate for the amount of charge to be lost by the off-leak current, it is necessary to employ a depletion transistor with a sufficiently large driving capability. This in turn requires an increase in the driving capability of an enhancement transistor in order to sufficiently lower the memory cell power supply. With the approach disclosed in FIG. 1 of Japanese Laid-Open Patent Publication No. 55-64686, the through current flowing through the inverter including a depletion transistor and an enhancement transistor connected in series together increases, thereby increasing the power consumption. Another problem is that increasing the driving capability of the transistors will increase the layout area.
Japanese Laid-Open Patent Publication No. 55-64686 also fails to take measures to optimally compensate for the leak current depending on the arrangement of the memory cell array, the transistor characteristics, the operating power supply voltage, the temperature condition, etc. Therefore, unless the power supply of the memory cell is controlled appropriately depending on the arrangement of the memory cell array, the transistor characteristics, the operating power supply voltage, the temperature condition, etc., the power consumption and the layout area will increase.